// module name: main_controller
// author: yangtao2019
// date: 2021.07.11

`timescale 1ns / 1ps

module main_controller(
    input[6:0] opcode,
    input ZeroSign,
    output Branch,
    output MemRead,   
    output MemtoReg,   
    output ALUOp1,
    output ALUOp0,   
    output MemWrite,    
    output ALUSrc,   
    output RegWrite,
    output ALUNum1Sec1,
    output ALUNum1Sec0,
    output PCSrc1,
    output PCSrc0,
    output Jalx 
);
    // all 8 Signs are grapped toghter
    wire [7:0] Signs;
    assign Signs = {ALUSrc, MemtoReg, RegWrite, MemRead,
                    MemWrite, Branch, ALUOp1, ALUOp0};
    
    // and given value together, while true table see book P183
    assign Signs =  (opcode==7'b011_0011)?  8'b0010_0010:   // R type
                    (opcode==7'b000_0011)?  8'b1111_0000:   // ld(I type)
                    (opcode==7'b001_0011)?  8'b101x_x000:   // addi(I type)
                    (opcode==7'b010_0011)?  8'b1x00_1000:   // sd(S type)
                    (opcode==7'b110_0011)?  8'b0x00_0101:   // beq(B type)
                    (opcode==7'b0x1_0111)?  8'b1x00_1011:   // lui, auipc(U type)
                    (opcode==7'b110_x111)?  8'bx010_00xx:   // jal, jalr(J type)
                                            8'b0000_0000;   // illegal opcode
    
    assign {ALUNum1Sec1, ALUNum1Sec0} = (opcode==7'b011_0111) ? 2'b01 : // lui(U type)
                                        (opcode==7'b001_0111) ? 2'b1x : // auipc(U type)
                                                                2'b00 ; // defualt value

    assign {PCSrc1, PCSrc0} = (opcode==7'b110_1111)?  2'b10 : // jal(J type)
                              (opcode==7'b110_0111)?  2'b11 : // jalr(J type)
                                     {1'b0, Branch&ZeroSign}; // 01 for B and 00 for no-jump

    assign Jalx =   (opcode==7'b110_x111)?  1'b1 : // J type
                                            1'b0 ; // others
                                    

endmodule